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lt 4275 1 4275f typical a pplica t ion fea t ures descrip t ion ltpoe ++ /poe + /poe pd controller the lt ? 4275 is a pin-for-pin compatible family of ieee 802.3 and ltpoe ++ powered device (pd) controllers. the lt4275 a employs a proprietary ltpoe ++ classification scheme, delivering 38.7w, 52.7w, 70 w or 90 w of power at the pd rj45 connector. the lt4275a is fully compat- ible with ieee 802.3. the lt4275b is an ieee 802.3at compliant, type 2 (poe + ) pd delivering up to 25.5 w. the lt4275c is an ieee 802.3 af compliant, type 1 ( poe) pd delivering up to 13w. the lt4275 internal charge pump provides an n-channel mosfet solution, eliminating a larger and more costly p-channel mosfet. a low r ds(on) mosfet also maxi- mizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. startup inrush current is adjustable with an external capacitor. the lt4275 also includes a power good output, on-board signature resistor, undervoltage lockout, and thermal protection. the lt4275 a/ lt4275 b drives a single opto - coupler to indicate the power level of the attached pse. pin-selectable sup- port for non-standard low voltage operation is provided. auxiliary power override is supported with the aux pin. the lt4275a can be configured to support all possible ltpoe ++ , 802.3 at and 802.3 af power levels with external component changes. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and ltpoe ++ and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltpoe ++ 90w powered device interface a pplica t ions n ieee 802.3af/at and ltpoe ++ ? powered device (pd) controller n ltpoe ++ supports power levels up to 90w n lt4275a supports all of the following standards: n ltpoe ++ 38.7w, 52.7w, 70w and 90w n ieee 802.3at 25.5w compliant n ieee 802.3af up to 13w compliant n lt4275b is ieee 802.3at/af compliant n lt4275c is ieee 802.3af compliant n 100v absolute maximum input voltage n wide junction temperature range (C40 c to 125 c) n overtemperature protection n integrated signature resistor n external hot swap? n-channel mosfet for lowest power dissipation and highest system efficiency n programmable aux power support as low as 9v n optional support of non-standard low voltage poe n available in 10-lead msop and 3mm 3mm dfn packages n high power wireless data systems n outdoor security camera equipment n commercial and public information displays n high temperature industrial applications lt4275 family max delivered power lt4275 grade a b c ltpoe ++ 90w l ltpoe ++ 70w l ltpoe ++ 52.7w l ltpoe ++ 38.7w l 25.5w l l 13w l l l lt4275a vport hsgate gnd 4275 ta01a ieeeuvlo hssrc aux rclass rclass ++ r cls++ pwrgd t2p r cls c pd 0.1f v port data pair spare pair run 47nf 3.3k fdmc86102 v in v out + ? isolated power supply opto pse type (to p) + ? ~ ~ + ? ~ ~ + c port v aux (9v to 60v)
lt 4275 2 4275f a bsolu t e maxi m u m r a t ings vport , hssrc voltages ......................... C 0.3 v to 100 v hsgate current .................................................. 20 ma ieeeuvlo , rclass, rcl ass ++ voltages ....... C 0.3 v to 8v ( and vport ) aux current ........................................................ 1 .4 ma t2p , pwrgd voltage ............................... C 0.3 v to 100 v t2p , pwrgd current ............................................... 5 ma (notes 1, 3) o r d er i n f or m a t ion lead free finish tape and reel part marking* max pd power package description temperature range lt4275aidd#pbf lt4275aidd#trpbf lgbs 90w 10-lead (3mm 3mm) plastic dfn C40c to 85c lt4275ahdd#pbf lt4275ahdd#trpbf lgbs 90w 10-lead (3mm 3mm) plastic dfn C40c to 125c lt4275aims#pbf lt4275aims#trpbf ltgbt 90w 10-lead plastic msop C40c to 85c lt4275ahms#pbf lt4275ahms#trpbf ltgbt 90w 10-lead plastic msop C40c to 125c lt4275bidd#pbf lt4275bidd#trpbf lgbv 25.5w 10-lead (3mm 3mm) plastic dfn C40c to 85c lt4275bhdd#pbf lt4275bhdd#trpbf lgbv 25.5w 10-lead (3mm 3mm) plastic dfn C40c to 125c lt4275bims#pbf lt4275bims#trpbf ltgbw 25.5w 10-lead plastic msop C40c to 85c lt4275bhms#pbf lt4275bhms#trpbf ltgbw 25.5w 10-lead plastic msop C40c to 125c lt4275cidd#pbf lt4275cidd#trpbf lgbx 13w 10-lead (3mm 3mm) plastic dfn C40c to 85c lt4275chdd#pbf lt4275chdd#trpbf lgbx 13w 10-lead (3mm 3mm) plastic dfn C40c to 125c lt4275cims#pbf lt4275cims#trpbf ltgby 13w 10-lead plastic msop C40c to 85c lt4275chms#pbf lt4275chms#trpbf ltgby 13w 10-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 vport hsgate hssrc pwrgd t2p/nc* ieeeuvlo aux rclass rclass ++ /nc* gnd t jmax = 150c, jc = 5c/w exposed pad (pin 11) is gnd, must be soldered to pcb gnd 1 2 3 4 5 ieeeuvlo aux rclass rclass ++ /nc* gnd 10 9 8 7 6 vport hsgate hssrc pwrgd t2p/nc* top view ms package 10-lead plastic msop t jmax = 150c, jc = 45c/w * rclass ++ is not connected in the lt4275b/c versions. t2p is not connected in the lt4275c version. p in c on f igura t ion operating junction temperature range ( note 4) lt 4275 ai / lt 4275 bi / lt 4275 ci .............. C 40 c to 85 c lt 4275 ah / lt 4275 bh / lt 4275 ch ....... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec .) .................. 30 0 c
lt 4275 3 4275f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units vport operating input voltage at vport pin l 23 60 v v sig vport signature range at vport pin l 1.5 10 v v class vport classification range at vport pin l 12.5 21 v v mark vport mark range at vport pin, preceded by v class l 5.6 10 v vport aux mode range at vport pin, aux > v auxt l 8 60 v signature/class hysteresis window l 1.0 v v reset reset threshold l 2.6 5.6 v v hson hot swap turn-on voltage ieeeuvlo = 0v ieeeuvlo open l l 35 27 37 29 v v v hsoff hot swap turn-off voltage ieeeuvlo = 0v ieeeuvlo open l l 30 21.5 31 22.5 v v hot swap on/off hysteresis window l 3 v supply current supply current vport = hssrc = 57v l 2 ma supply current during classification vport = 17.5v, rclass and rclass ++ open l 0.4 0.7 1.1 ma supply current during mark event v mark l 0.5 2.2 ma signature and classification signature resistance v sig (note 2) l 23.7 24.4 25.2 k signature resistance during mark event v mark (note 2) l 5.8 8.3 11 k v rcls rclass/rclass ++ operating voltage C10ma i rclass C36ma, v class l 1.32 1.40 1.43 v classification stability time vport step to 17.5v, rclass = 34.8 l 2 ms analog/digital interface v auxt aux threshold l 6.1 6.3 6.5 v i auxh aux pin hysteresis current aux = 6.1v l 4 5.8 8 a t2p output low 1ma load (lt4275a/lt4275b only) l 0.8 v pwrgd output low 1ma load l 0.8 v pwrgd leakage current p wrgd = 60v l 5 a t2p leakage current t2p = 60v l 5 a hot swap control i gpu hsgate pull-up current v hsgate C v hssrc = 5v, v port > 42v, out of pin l 18 22 27 a v goc hsgate open circuit voltage v hsgate C v hssrc , 0a to 10a load with respect to hssrc l 10 18 v hsgate pull-down current v hsgate C v hssrc = 5v l 200 a timing f t2p t2p frequency after pwrgd valid, if ltpoe ++ pse is mutually identified l 690 840 990 hz note 3: all voltages with respect to gnd unless otherwise noted. positive currents are into pins; negative currents are out of pins unless otherwise noted. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
lt 4275 4 4275f typical p er f or m ance c harac t eris t ics signature resistance vs input voltage vport hot swap thresholds reset threshold pwrgd, t2p output low voltage vs current vport classification thresholds t2p frequency vport current vs vport voltage 25k detection range vport hot swap thresholds supply current during power-on vport voltage (v) 0 vport current (ma) 0.2 0.3 0.4 0.5 0.1 0 8 4275 g01 10 6 2 4 t = ?40c t = 25c t = 75c t = 125c temperature (c) ?50 vport voltage (v) 32 33 34 35 36 37 31 30 100 4275 g02 125 75 ?25 50250 ieeeuvlo = 0v hot swap off hot swap on vport voltage (v) 35 supply current (ma) 1.0 1.5 2.0 0.5 0 55 4275 g03 60 50 40 45 t = ?40c t = 25c t = 75c t = 125c vport voltage (v) 1 signature resistance (k) 25.25 25.75 26.25 24.75 24.25 23.75 4275 g04 9 7 3 5 t = ?40c t = 25c t = 75c t = 125c temperature (c) ?50 vport voltage (v) 24.5 26.0 27.5 29.0 23.0 21.5 100 4275 g05 125 75 ?25 50250 ieeeuvlo = float hot swap off hot swap on temperature (c) ?50 vport voltage (v) 3.6 4.1 5.1 4.6 5.6 3.1 2.6 100 4275 g06 125 75 ?25 50250 current (ma) 0 voltage (v) 2 3 4 1 0 4 4275 g07 5 3 1 2 t = ?40c t = 25c t = 75c t = 125c temperature (c) ?50 vport voltage (v) 11.0 11.5 12.0 12.5 10.5 10.0 100 4275 g08 125 75 ?25 50250 detect or mark to class class to mark temperature (c) ?50 t2p frequency (hz) 840 740 890 940 990 790 690 100 4275 g09 125 75 ?25 50250
lt 4275 5 4275f p in func t ions ieeeuvlo (pin 1): hot swap turn-on threshold level control. connect to ground for ieee compliant turn-on and turn-off ( uvlo) voltage thresholds. leave open for lower turn-on and turn-off voltage thresholds. aux (pin 2): auxiliary sense. assert aux via a resistive divider from the auxiliary power input to set the voltage at which the auxiliary supply takes over. asserting aux pulls down hsgate, disconnects the signature resistor, disables classification and floats the pwrgd pin. the aux pin sinks i auxh when below its threshold voltage of v auxt to provide hysteresis. tie to gnd when not used. rclass (pin 3): programmable poe classification resis- tor. see table 1. rclass ++ ( pin 4, lt4275 a only): programmable ltpoe ++ classification resistor. this pin is not connected on the lt4275b/lt4275c. see table 1. gnd (pin 5): ground pin. must be soldered to pcb gnd. t2p (pin 6, lt4275a/lt4275b only): pse type indica- tor, open-drain output. t2p floats for a 13 w pse. t2p pulls down for a 25.5 w pse. t2p pulls down at f t2p with a 50% ( typical) duty cycle to indicate the presence of an ltpoe ++ pse. t2p is valid after p wrgd is active. this pin is not connected on the lt4275c. see the applications information section for behavior when using the aux pin. pwrgd ( pin 7): power good indicator, open - drain output. pulls down during v class and inrush. hssrc (pin 8): external hot swap mosfet source. con- nect to source of the external mosfet. hsgate (pin 9): external hot swap mosfet gate control, output. connect to gate of the external mosfet. vport ( pin 10): pd interface upper power rail and external hot swap mosfet drain connection. exposed pad ( pin 11, dfn package only): gnd. must be soldered to pcb gnd. b lock diagra m 4275 bd control logic classification logic voltage and current references charge pump overtemp on gnd v port v port v goc 6.3v 1.4v 1.4v + ? + ? en + ? en v port vport aux rclass rclass++ t2p hssrc hsgate pwrgd ieeeuvlo
lt 4275 6 4275f a pplica t ions i n f or m a t ion o verview power over ethernet ( poe) continues to gain popularity as products take advantage of dc power and high speed data available from a single rj45 connector. powered device ( pd ) equipment vendors are running into the 25.5 w power limit established by the ieee 802.3 standard. the lt4275a allows higher power while maintaining backwards com- patibility with existing pse systems. the lt4275 utilizes a low r ds(on) n-channel mosfet to maximize efficiency and delivered power. heat is also reduced, easing thermal design. m odes of o pera tion the lt4275 has several modes of operation depending on the input voltage sequence applied to the vport pin. these modes include 25k signature detection, classifica - tion, mark, inrush and powered on. d etection during detection, the pse looks for a 25 k signature resistor which identifies the device as a pd. the pse will apply two voltages in the range of 2.8 v to 10 v and measure the corresponding currents. figure 1 shows the detection voltages. the pse calculates the signature resistance using a ?v/?i measurement technique. the lt4275 presents its precision, temperature-compen- sated 24.4 k resistor between the vport and gnd pins, allowing the pse to recognize a pd is present and request- ing power to be applied. the lt4275 signature resistor is smaller than 25k to compensate for the additional series resistance introduced by the ieee required bridge. c lassifica tion the detection/classification process varies depending on whether the pse is type 1, type 2, or ltpoe ++ . a type 2 pse may use type 1 classification signaling and later renegotiate a higher power classification with the pd over the data layer. a type 1 pse, after a successful detection, may apply a classification probe voltage of 15.5 v to 20.5 v and mea- sure current. a type 2 pse may declare the availability of high power by performing 2-event ( physical layer) classification or by communicating over the ( data link layer) high speed data line. a type 2 pd must recognize both types of communication. since layer 2 communications takes place directly between the pse and the pd application, the lt4275a/lt4275b responsibility ends with supporting 2-event classification. in 2- event classification, a type 2 pse probes for power classification twice as shown in figure 2. the lt4275a or lt4275b recognizes this and pulls the t2p pin down to signal the load that type 2 power is available. if an lt4275a senses an ltpoe ++ pse it alternates between pulling t2p down and floating t2p at a rate of f t2p . figure 1. type 1 detect/class signaling waveform figure 2. type 2 detect/class signaling waveform 4275 f01 v port v hson v hsoff v classmin v sigmax v sigmin v reset detect class power on 4275 f01 v port v hson v hsoff v classmin v sigmax v sigmin v reset detect 1st class 1st mark 2nd mark 2nd class power on
lt 4275 7 4275f a pplica t ions i n f or m a t ion table 1. classification codes, power levels and resistor selection class pd power available pd type nominal class current lt4275 grade capability resistor a b c r cls r cls ++ 0 13w type 1 <0.4ma ? ? ? open open 1 3.84w type 1 10.5ma ? ? ? 140 open 2 6.49w type 1 18.5ma ? ? ? 76.8 open 3 13w type 1 28ma ? ? ? 49.9 open 4 25.5w type 2 40ma ? ? 34.8 open 4* 38.7w ltpoe ++ 40ma ? open 34.8 4* 52.7w ltpoe ++ 40ma ? 140 46.4 4* 70w ltpoe ++ 40ma ? 76.8 64.9 4* 90w ltpoe ++ 40ma ? 49.9 118 *an ltpoe ++ pd will be classified as class 4 by an ieee 802.3 compliant pse. lt p oe ++ c lassifica tion the lt4275a allows higher power allocation while main- taining backwards compatibility with existing pse systems by extending the classification signaling of ieee 802.3. linear technology pse controllers that are capable of ltpoe ++ are listed in the related parts section. ieee pses will classify an ltpoe ++ pd as a type 2 pd. s igna ture c orrup t d uring m ark during the mark state, the lt4275 presents <11 k to the port as required by the ieee specification. i nrush and p owered o n once the pse detects and optionally classifies the pd, the pse then powers on the pd. when the port voltage rises above the v hson threshold, it begins to source i gpu out of the hsgate pin. this current flows into an external capaci- tor (c gate in figure 3) that causes a voltage to ramp up the gate of the external mosfet. the external mosfet acts as a source follower and ramps the voltage up on the output bulk capacitor (c port in figure 3) thereby determining the inrush current (i inrush in figure 3). to meet ieee requirements, design i inrush to be approxi- mately 100ma. see equation below: i inrush = i gpu ? c port c gate the lt4275 internal charge pump provides an n-channel mosfet solution, eliminating a larger and more costly p-channel fet. the low r ds(on) mosfet also maximizes lt4275a hsgate gnd 4275 f03 vport hssrc c gate 3.3k + c port vport i inrush figure 3. programming i inrush power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. the pwrgd pin is held low by its open drain output until hsgate charges up to approximately 7 v above hssrc. the pwrgd pin is used to hold off the isolated power supply until inrush is complete and the external mosfet is fully enhanced. the hsgate pin will remain high and the pwrgd pin pulled down until the port voltage falls below v hsoff or the aux pin is above v auxt . a uxiliar y s uppl y o verride if the aux pin is held above v auxt , the lt4275 enters auxiliary power supply override mode. in this mode the signature resistor is disconnected, classification is disabled, hsgate is pulled down, and the pwrgd pin is allowed to float. the t2p pin pulls down on the lt4275a/ lt4275b when no r cls ++ resistor is present. the t2p pin alternates between pulling down and floating at f t2p on the lt4275a when the r cls ++ resistor is present.
lt 4275 8 4275f a pplica t ions i n f or m a t ion the aux pin allows for setting the auxiliary supply turn on (v auxon ) and turn off (v auxoff ) voltage thresholds. the auxiliary supply hysteresis voltage (v auxhys ) is set by sinking current (i auxh ) only when the aux pin voltage is less than v auxt . use the following equations to set v auxon and v auxoff via r1 and r2 in figure 4. figure 4. aux threshold and hysteresis calculation transient voltage suppressor the lt4275 specifies an absolute maximum voltage of 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can routinely see excessive peak voltages. to protect the lt4275, install a unidirectional transient voltage suppres- sor ( tvs ) such as an smaj58a between the port voltage and gnd. this tvs must be mounted near the lt4275. for extremely high cable discharge and surge protection contact linear technology applications. classification resistor (r cls and r cls ++ ) the r cls resistors set the classification load current cor- responding to the pd power classification. select the value of r cls from table 1 and connect the resistor between the rclass pin and gnd, or float the rclass pin if class 0 is required. the resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit. for ltpoe ++ use the lt4275a and select the value of r cls ++ from table 1 in addition to r cls . power good interface the lt4275 provides a power good signal ( pwrgd) to simplify the isolated power supply design. the power good signal is used to delay isolated power supply startup until the c port capacitor is fully charged. exposed pad the lt4275a/lt4275b/lt4275c dfn package has an exposed pad that is internally electrically connected to gnd. the exposed pad may only be connected to gnd on the printed circuit board. l a yout c onsidera tions avoid excessive parasitic capacitance on the rclass pin and place resistor r cls close to the lt4275. for the lt4275a, place r cls ++ nearby as well. it is strictly required for maximum protection to place the input capacitor (c pd ) and transient voltage suppressor as close to the lt4275 as possible. lt4275a gnd 4275 f04 aux r1 v aux + ? r2 r1 = v auxon ? v auxoff i auxh = v auxhys i auxh r2 = r1 v auxoff v auxt ? 1 ? ? ? ? ? ? r1 v aux(max) ? v auxt 1.4ma t hermal p rotection the ieee 802.3 specification requires a pd to withstand any applied voltage from 0 v to 57 v indefinitely. during classification, however, the power dissipation in the lt4275 may be as high as 1.5 w. the lt4275 can easily tolerate this power for the maximum ieee timing but will overheat if this condition persists abnormally. the lt4275 includes a thermal protection feature which protects itself from excessive heating. if the junction temperature exceeds the overtemperature threshold, the lt4275 pulls down the hsgate and pwrgd pins and disables classification. e xternal i nterf ace and c omponent s election input diode bridge t he input diode bridge introduces a voltage drop that affects the voltage range for each mode of operation. the lt4275 is designed to tolerate these voltage drops. the voltages shown in the electrical specifications are measured at the lt4275 package pins. input capacitor a 0.1 f capacitor is needed from vport to gnd to meet an input impedance requirement in ieee 802.3.
lt 4275 9 4275f typical a pplica t ions ieee 802.3af (type 1) 13w powered device lt4275a/lt4275b/lt4275c vport hsgate gnd 4275 ta02 ieeeuvlo hssrc rclass rclass ++ pwrgd t2p aux r cls c pd 0.1f run 47nf 3.3k fdn8601 smaj58a v in v out + ? isolated power supply + ? ~ ~ + ? ~ ~ ethernet magnetics + c port v port lt4275a/lt4275b vport hsgate gnd 4275 ta03 ieeeuvlo hssrc rclass rclass ++ pwrgd t2p aux r cls c pd 0.1f run 47nf 3.3k fdn8601 smaj58a v in v out + ? isolated power supply opto pse type (to p) + ? ~ ~ + ? ~ ~ ethernet magnetics + c port v port ieee 802.3at (type 2) 25.5w powered device ltpoe ++ 38.7w to 90w powered device lt4275a vport hsgate gnd 4275 ta04 ieeeuvlo hssrc rclass rclass ++ r cls++ pwrgd t2p aux r cls c pd 0.1f run 47nf 3.3k fdmc86102 smaj58a v in v out + ? isolated power supply opto pse type (to p) + ? ~ ~ + ? ~ ~ wrth 749022016 + c port v port
lt 4275 10 4275f p ackage descrip t ion dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer
lt 4275 11 4275f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002)
lt 4275 12 4275f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0712 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc4257-1 ieee 802.3af pd interface controller internal 100v, 400ma switch, dual current limit, programmable class ltc4263 single ieee 802.3af pse controller internal fet switch ltc4265 ieee 802.3at pd interface controller internal 100v, 1a switch, 2-event classification recognition ltc4266 quad ieee 802.3at poe pse controller with programmable i cut /i lim , 2-event classification ltc4266a quad ltpoe ++ pse controller provides up to 90w. backwards compatible with ieee 802.3af and ieee 802.3at pds. with programmable i cut /i lim , 2-event classification ltc4266c quad ieee 802.3af pse controller with programmable i cut /i lim , 1-event classification ltc4267-3 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, programmable class, 300khz constant frequency pwm LTC4269-1 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable class, synchronous no-opto flyback controller, 50khz to 250khz, aux support ltc4269-2 ieee 802.3af pd interface with integrated forward switching regulator 2-event classification, programmable class, synchronous forward controller, 100khz to 500khz, aux support ltc4270/ ltc4271 12-port poe/poe + /ltpoe ++ pse controller transformer isolation, supports ieee 802.3af, ieee 802.3at and ltpoe ++ pds ltc4274 single ieee 802.3at poe pse controller with programmable i cut /i lim , 2-event classification ltc4274a single ltpoe ++ pse controller provides up to 90w. backwards compatible with ieee 802.3 pds. with programmable i cut /i lim , 2-event classification ltc4274c single ieee 802.3af pse controller with programmable i cut /i lim , 1-event classification ltc4278 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable class, synchronous no-opto flyback controller, 50khz to 250khz, 12v aux support ltc4290/ ltc4271 8-port poe/poe + /ltpoe ++ pse controller transformer isolation, supports ieee 802.3af, ieee 802.3at and ltpoe ++ pds 25w pd solution with 12vdc and 24 vac auxiliary input lt4275a/lt4275b vport hsgate 4275 ta05 hssrc aux rclass ieeeuvlo gnd pwrgd t2p 34.8 931k smaj58a 158k 47nf 3.3k fdn8601 mmsd4148 mmsd4148 (2plcs) b2100 (4plcs) opto pse type (to p) to isolated power supply run to isolated power supply 8.2 0.1f 0.1f + 470f v aux 9v to 57vdc or 24vac ~ ~ wrth 7499511001 1?12 to phy b2100 (8plcs) 13 15 16 14

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